Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers

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概要

• 論文の詳細を見る
• 2012-08-01

著者

• Masui Shoichi

  Tohoku University

• Masui Shoichi

  Tohoku Univ. Sendai‐shi Jpn

• Lee Jun

  Tohoku University

• Xu Zule

  Tohoku University

関連論文

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• Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g_m/I_D Lookup Table
• Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL
• Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers

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