Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
スポンサーリンク
概要
- 論文の詳細を見る
- 2011-12-01
著者
-
Chen Liang-bi
Department Of Computer Science And Engineering National Sun Yat-sen University
-
LI Katherine
Department of Computer Science and Engineering, National Sun Yat-Sen University
-
PAI Chih-Yun
Department of Computer Science and Engineering, National Sun Yat-Sen University
-
Li Katherine
Department Of Computer Science And Engineering National Sun Yat-sen University
-
Pai Chih-yun
Department Of Computer Science And Engineering National Sun Yat-sen University
関連論文
- HPChecker : An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
- A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
- Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
- Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
- An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip