A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

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概要

• 論文の詳細を見る

• 3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.

• （社）電子情報通信学会の論文
• 2009-12-01

著者

• HUANG Ing-Jer

  Department of Computer Science and Engineering, National Sun Yat-Sen University

• Huang Ing-jer

  Department Of Computer Science And Engineering National Sun Yat-sen University

• CHEN Liang-Bi

  Department of Computer Science and Engineering, National Sun Yat-Sen University

• YEH Chi-Tsai

  Department of Information Management, Shih-Chien University

• CHEN Hung-Yu

  Department of Computer Science and Engineering, National Sun Yat-Sen University

• Chen Liang-bi

  Department Of Computer Science And Engineering National Sun Yat-sen University

• Chen Hung-yu

  Department Of Computer Science And Engineering National Sun Yat-sen University

• Yeh Chi-tsai

  Department Of Information Management Shih-chien University

• Chen Liang‐bi

  National Sun Yat‐sen Univ. Kaohsiung Twn

• Huang Ing‐jer

  National Sun Yat‐sen Univ. Kaohsiung Twn

関連論文

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• HPChecker : An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
• A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
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• Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
• An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip

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