Chen Liang-bi | Department Of Computer Science And Engineering National Sun Yat-sen University
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概要
- CHEN Liang-Biの詳細を見る
- 同名の論文著者
- Department Of Computer Science And Engineering National Sun Yat-sen Universityの論文著者
関連著者
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Chen Liang-bi
Department Of Computer Science And Engineering National Sun Yat-sen University
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CHEN Liang-Bi
Department of Computer Science and Engineering, National Sun Yat-Sen University
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Li Katherine
Department Of Computer Science And Engineering National Sun Yat-sen University
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HUANG Ing-Jer
Department of Computer Science and Engineering, National Sun Yat-Sen University
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Huang Ing-jer
Department Of Computer Science And Engineering National Sun Yat-sen University
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LI Katherine
Department of Computer Science and Engineering, National Sun Yat-Sen University
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HO Yingchieh
Department of Electrical and Control Engineering, National Chiao Tung University
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JU Jiun-Cheng
Department of Computer Science and Engineering, National Sun Yat-Sen University
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WANG Chien-Chou
Department of Computer Science and Engineering, National Sun Yat-Sen University
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YEH Chi-Tsai
Department of Information Management, Shih-Chien University
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CHEN Hung-Yu
Department of Computer Science and Engineering, National Sun Yat-Sen University
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Chen Hung-yu
Department Of Computer Science And Engineering National Sun Yat-sen University
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Yeh Chi-tsai
Department Of Information Management Shih-chien University
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Ju Jiun-cheng
Department Of Computer Science And Engineering National Sun Yat-sen University
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Chen Liang‐bi
National Sun Yat‐sen Univ. Kaohsiung Twn
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Wang Chien-chou
Department Of Computer Science And Engineering National Sun Yat-sen University
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Huang Ing‐jer
National Sun Yat‐sen Univ. Kaohsiung Twn
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PAI Chih-Yun
Department of Computer Science and Engineering, National Sun Yat-Sen University
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Pai Chih-yun
Department Of Computer Science And Engineering National Sun Yat-sen University
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HO Yingchieh
Department of Electrical Engineering, National Dong-Hwa University
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YANG Yu-Wei
Department of Laboratory,Mianyang Central Hospital
著作論文
- HPChecker : An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
- A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
- Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
- Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
- An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip