Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption
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概要
- 論文の詳細を見る
A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.
- （社）電子情報通信学会の論文
- 2008-08-01
著者
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ABE Koki
Department of Computer Science, The University of Electro-Communications
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Abe Koki
Department Of Computer Science
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ISHIHARA Nozomi
Department of Computer Science, The University of Electro-Communications
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Ishihara Nozomi
Department Of Computer Science The University Of Electro-communications
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