Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

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概要

• 論文の詳細を見る

• This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.

• 2008-04-01

著者

• Fanucci Luca

  Univ. Pisa Pisa Ita

• Fanucci Luca

  Department Of Information Engineering Of The University Of Pisa

• Fanucci Luca

  Cnr-ieiit

• Saponara Sergio

  Univ. Of Pisa Pisa Ita

• Saponara Sergio

  Department Of Information Engineering University Of Pisa

• Fanucci Luca

  Department Of Information Engineering University Of Pisa Via G. Caruso

• Saponara Sergio

  Department Of Information Engineering University Of Pisa Via G. Caruso

• TERRENI Pierangelo

  Department of Information Engineering, University of Pisa Via G. Caruso

• Terreni Pierangelo

  Department Of Information Engineering University Of Pisa Via G. Caruso

関連論文

• Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
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• High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes(VLSI Architecture, VLSI Design and CAD Algorithms)

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