High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes(VLSI Architecture, <Special Section>VLSI Design and CAD Algorithms)
スポンサーリンク
概要
- 論文の詳細を見る
As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoder on 0.18μm standard cells CMOS technology showed remarkable performances : small implementation loss (0.2dB down to BER=10^<-8>), low latency (less than 6.0μs), high useful throughput (up to 940Mbps) and low complexity (about 375 Kgates).
- 社団法人電子情報通信学会の論文
- 2005-12-01
著者
-
Fanucci Luca
Univ. Pisa Pisa Ita
-
Fanucci Luca
Department Of Information Engineering Of The University Of Pisa
-
ROVINI Massimo
Department of Information Engineering of the University of Pisa
-
ROSSI Francesco
Department of Information Engineering of the University of Pisa
関連論文
- Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
- Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems(Adaptive Signal Processing, Recent Advances in Circuits and Systems-Part 1)
- Power Optimization of an 8051-Compliant IP Microcontroller(Low-Power LSI and Low-Power IP)
- High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes(VLSI Architecture, VLSI Design and CAD Algorithms)
- A Low-Complexity and High-Resolution Algorithm for the Magnitude Approximation of Complex Numbers(VLSI Design Technology and CAD)
- Multi-Code Multi-Carrier CDMA Modulation with Adaptive Bit-Loading for VDSL Modems(Digital Signal Processing)