Power Optimization of an 8051-Compliant IP Microcontroller(<Special Section>Low-Power LSI and Low-Power IP)

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概要

• 論文の詳細を見る

• Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• SAPONARA Sergio

  University of Pisa

• Fanucci Luca

  Univ. Pisa Pisa Ita

• Fanucci Luca

  Cnr-ieiit

• Saponara Sergio

  Univ. Of Pisa Pisa Ita

• Fanucci Luca

  Department Of Information Engineering University Of Pisa Via G. Caruso

• Saponara Sergio

  Department Of Information Engineering University Of Pisa Via G. Caruso

• MORELLO Alexander

  University of Pisa

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