Data Driven Power Saving for DCT/IDCT VLSI Macrocell(VLSI Design Technology and CAD)

スポンサーリンク

概要

• 論文の詳細を見る

• In this letter a low-complexity and low-power realization of the 2D discrete-cosine-transform and its inverse (DCT/IDCT) is presented. A VLSI circuit based on the Chen algorithm with the distributed arithmetic approach is described. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the circuit power consumption. To this aim, input signal statistics have been extracted from H.263/MPEG verification models. Finally, circuit performance is compared to known software solutions and dedicated full-custom ones.

• 社団法人電子情報通信学会の論文
• 2002-07-01

著者

• Fanucci L

  Ieiit National Res. Council Pisa Ita

• Saponara Sergio

  Department Of Information Engineering University Of Pisa

• Fanucci Luca

  Csmdr National Research Council

関連論文

• Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
• Data Driven Power Saving for DCT/IDCT VLSI Macrocell(VLSI Design Technology and CAD)

スポンサーリンク