Tinv Scaling and Jg Reducing for nMOSFET with HfSi_x/HfO_2 Gate Stack by Interfacial Layer Formation Using Ozone Water Treatment Process
スポンサーリンク
概要
- 論文の詳細を見る
- 2007-09-19
著者
-
ANDO T.
Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporatio
-
HIRANO T.
Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporatio
-
TAI K.
Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporatio
-
WATANABE K.
Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporatio
-
IWAMOTO H.
Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporatio
-
KADOMURA S.
Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporatio
-
Kadomura S.
Technology Development Division Semiconductor Business Group Sony Corporation
-
OSHIYAMA I.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
YAMAGUCHI S.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TANAKA K.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
HAGIMOTO Y.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
UEMURA T.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
YAMAMOTO R.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
KANDA S.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
WANG J.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TATESHITA Y.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
WAKABAYASHI H.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TAGAWA Y.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TSUKAMOTO M.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
SAITO M.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
OSHIMA M.
Graduate School of Engineering, University of Tokyo
-
TOYODA S.
Graduate School of Engineering, University of Tokyo
-
NAGASHIMA N.
Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TAI K.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
HIRANO T.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
OSHIYAMA I.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TATESHITA Y.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TAGAWA Y.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
TSUKAMOTO M.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
IWAMOTO H.
Technology Development Division, Semiconductor Business Group, Sony Corporation
-
Tateshita Y.
Technology Development Division Semiconductor Business Group Sony Corporation
-
Oshiyama I.
Technology Development Division Semiconductor Business Group Sony Corporation
-
Tai K.
Technology Development Division Semiconductor Business Group Sony Corporation
-
Kazi S.
Technology Development Division Semiconductor Business Group Sony Corporation
-
Iwamoto H.
Technology Development Division Semiconductor Business Group Sony Corporation
-
Nagashima N.
Technology Development Division Semiconductor Business Group Sony Corporation
-
Hagimoto Y.
Semiconductor Technology Development Division Semiconductor Business Group Sony Corporation
関連論文
- PMOSFET Vth Modulation Technique using Fluorine Treatment through ALD-TiN Suitable for CMOS Devices
- Application of HfSiON to Deep Trench Capacitors of Sub-45nm Node Embedded DRAM
- Tinv Scaling and Jg Reducing for nMOSFET with HfSi_x/HfO_2 Gate Stack by Interfacial Layer Formation Using Ozone Water Treatment Process
- Gate Overlapped Raised Extension Structure (GORES) MOSFET by Using In-situ Doped Selective Si Epitaxy
- Impact of the Grain Size and Orientation of SrBi_2(Ta,Nb)_2O_9 Films on the Polarization for Nano-Scale FeRAMs