LDMOS Model for Device and Circuit Optimization

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概要

• 論文の詳細を見る
• 2007-09-19

著者

• Miura Mattausch

  Hiroshima University

• MATTAUSCH H.

  Research Center for Nanodevices and Systems, Hiroshima University

• YOKOMICHI M.

  Hiroshima University

• MIYAKE M.

  Hiroshima University

• KAJIWARA T.

  Hiroshima University

• SADACHIKA N.

  Hiroshima University

• YUMISAKI A.

  Hiroshima University

• MATTAUSCH H.

  Hiroshima University

• Mattausch H.

  Research Center For Nanodevices And Systems Hiroshima University

関連論文

• LDMOS Model for Device and Circuit Optimization
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• Frequency Dependence of Measured MOSFET Distortion Characteristic
• Nearest-Euclidean-Distance Search Associative Memory with Fully Parallel Mixed Digital-Analog Match Circuitry
• Image-Scan Video Segmentation Architecture and FPGA Implementation

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