Large Reduction in Standby Power Consumption Achieved with Stress-controlled SRAM Cell Layout

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概要

• 論文の詳細を見る
• 2006-09-13

著者

• Sugimachi T.

  Fujitsu Limited

• Kihara F.

  Fujitsu Limited

• KUDO H.

  FUJITSU LABOTARORIES LIMITED

• ISHIKAWA K.

  FUJITSU LABOTARORIES LIMITED

• TANABE R.

  FUJITSU LABOTARORIES LIMITED

• FUKUTOME H.

  FUJITSU LABOTARORIES LIMITED

• MISHIMA Y.

  FUJITSU LABOTARORIES LIMITED

• SATOU S.

  FUJITSU LABOTARORIES LIMITED

• SUGII T.

  FUJITSU LABOTARORIES LIMITED

• OKAMOTO M.

  FUJITSU LIMITED

• YOSHIMURA M.

  FUJITSU LIMITED

• HASHIMOTO H.

  FUJITSU LIMITED

• OHTSUKI M.

  FUJITSU LIMITED

• Okamato M.

  Fujitsu Limited

• Sugii T.

  Fujitsu Laboratories Ltd.

関連論文

• Large Reduction in Standby Power Consumption Achieved with Stress-controlled SRAM Cell Layout
• Efficient Reduction of Standby Leakage Current in LSIs for Use in Mobile Devices
• Advanced I/O Technology using Laterally Modulated Channel MOSFET for 65-nm Node SoC
• Self-Aligned Control of Threshold Voltages in 0.1μm nMOSFETs
• Impact of Shallow Source/Drain on Scaling pMOSFETs below 0.1μm

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