New Guidelines of Optimizing SALICIDE Structure for High Speed CMOS LSI
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概要
- 論文の詳細を見る
- 1999-09-20
著者
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Suguro K.
Microelectronics Engineering Laboratory Toshiba Corporation Semiconductor Company
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Toyoshima Y.
Microelectronics Engineering Laboratory Toshiba Corporation Semiconductor Company
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MIYASHITA K.
Microelectronics Engineering Laboratory, Toshiba Corporation Semiconductor Company
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OHUCHI K.
Microelectronics Engineering Laboratory, Toshiba Corporation Semiconductor Company
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YOSHIMURA H.
Microelectronics Engineering Laboratory, Toshiba Corporation Semiconductor Company
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IINUMA T.
Microelectronics Engineering Laboratory, Toshiba Corporation Semiconductor Company
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Toyoshima Y.
Center For Semiconductor Research & Development Toshiba Corporation Semiconductor Company
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Ohuchi K.
Microelectronics Engineering Laboratory Toshiba Corporation Semiconductor Company
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Iinuma T.
Microelectronics Engineering Laboratory Toshiba Corporation Semiconductor Company
関連論文
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- Ultra Shallow Junction Formation for 80nm CMOS by Controlling Transient Enhanced Diffusion