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Yonsei University | 論文
- A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution(Electronic Circuits)
- Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems
- An Automatic Skin Allergy Test Using Fuzzy Image Processing
- Obesity paradox in Korean patients undergoing primary percutaneous coronary intervention in ST-segment elevation myocardial infarction
- Sharp pelvic dissection for abdominoperineal resection with pelvic autonomic nerve preservation for distal rectal cancer based upon anatomical and MRI knowledge
- SB-O8 Engineering biological circuits responsive to a small molecule(Section XI Systems Biotechnology/Metabolic Engineering)
- The Student Symposium on Future Photochemistry
- Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs
- An Offset Cancelled Winner-Take-All Circuit
- A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals
- 1λ-Deviation Compensation Scheme for Ultrasonic Positioning System(Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005))
- Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis(VLSI Design Technology and CAD)
- Burn scars treated by pinhole method using a carbon dioxide laser
- Fractional Error Estimation Technique of the Space-Based SAR Processor Using RDA(Sensing)
- Hybrid Concatenated Space-Time Coding Systems(Fundamental Theories)
- Hybrid Concatenated Space-Time Coding Systems
- Forward Link Capacity of a CDMA System in a Hierarchical Cell with Hard/Soft Handoffs
- A WDFT-Based Channel Estimator with Non-adaptive Linear Prediction in Non-sample Spaced Channels
- Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method
- A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters