A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution(Electronic Circuits)

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概要

• 論文の詳細を見る

• A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18μm CMOS process shows error-free operation for ±400ppm frequency offset. The chip occupies 165×255μm^2 and consumes 17.8mW.

• 社団法人電子情報通信学会の論文
• 2007-01-01

著者

• Choi Woo‐young

  Yonsei Univ. Seoul Kor

• CHOI Woo-Young

  Yonsei University

• SEONG Chang-Kyung

  Yonsei University

• LEE Seung-Woo

  Electronics and Telecommunications Research Institute

• Lee Seung‐woo

  Electronics And Telecommunications Research Institute

関連論文

• Linear Analysis of Feedforward Ring Oscillators
• A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator
• A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution(Electronic Circuits)
• Linear Analysis of Feedforward Ring Oscillators

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