Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• We present a scenario-aware bus functional modeling method which improves the accuracy of traditional methods without sacrificing the simulation run time. Existing methods focused on the behavior of individual IP (Intellectual Property) components and neglected the interplay effects among them, resulting in accuracy degradation from the system perspective. On the other hand, our method thoroughly considers such effects and increases the analysis accuracy by adopting control signal modeling and hierarchical stochastic modeling. Furthermore, our method minimizes the additional design time by reusing the simulation results of each IP component and an automated design flow. The experimental results show that the accuracy of our method is over 90% of RTL simulation in a multimedia SoC (System-on-Chip) design.

• 2007-04-01

著者

• Chung Sung

  Korea Univ. Seoul Kor

• Chung Eui-young

  Yonsei University

• Lee Hyuk‐jun

  Cisco Systems Incorporation

• Chung Eui‐young

  Yonsei Univ. Kor

• LEE Hyuk-Jun

  Cisco Systems Incorporation

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