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Silicon Systems Research Labs. | 論文
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- Uniform Raised-Salicide Technology for High-Performance CMOS Devices(Special Issue on Advanced Sub-0.1μm CMOS Devices)
- Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
- An Investigation on the Short Channel Effect for 0.1 μm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model
- Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET
- The Influence of the Device Miniaturization on the I_ Enhancement in the Intrinsic Silicon Body (i-body) SOI-MOSFET's
- A Study of the V_ Fluctuation for 25nm CMOS
- Simulation on A Novel Sub-0.1μm Body Driven SOI-MOSFET (BD-SOIMOS) for Small Logic Swing Operation
- Simulation on a Novel Body-Driven Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect-Transistor for Sub-0.1 μm Small Logic Swing Operation
- Analysis on the Threshold Voltage Fixing and the Floating-Body-Effect Suppression for 0.1μm Fully Depleted SOI-MOSFET
- Analysis of The Threshold Voltage Adjustment and Floating Body Effect Suppression for 0.1 μm Fully Depleted SOI-MOSFET
- Buried Insulator Engineering for sub-0.05μm Fully-Depleted SOI-MOSFET to Reduce the Drain Induced Barrier Lowering
- Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs
- Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET