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Inter-university Semiconductor Research Center (isrc):school Of Electrical Engineering And Computer | 論文
- Gate-All-Around Tunnel Field-Effect Transistor (GAA TFET) with Vertical Channel and n-doped Layer
- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
- Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
- Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Gate-All-Around Tunnel Field-Effect Transistor (GAA TFET) with Vertical Channel and n-doped Layer
- Dual-gate single-electron transistor with silicon nano wire channel and surrounding side gates (Special issue: Solid state devices and materials)
- Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Silicon-based dual-gate single-electron transistors for logic applications
- Synthesis of small diameter silicon nanowires on SiO_2 and Si3_N_4 surfaces
- Synthesis of small diameter silicon nanowires on SiO_2 and Si_3N_4 Surfaces