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Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo | 論文
- The in vitro osteogenetic characteristics of primary osteoblastic cells from a rabbit calvarium
- Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
- Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
- High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
- A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
- Alleviation of Additional Phase Noise in Saturated Optical Parametric Amplifier Based Signal Regenerator
- High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
- B-10-87 Alleviation of the Additional Phase Noise in a Saturated Fiber Optical Parametric Amplifier
- C-12-40 Effect of CMOS Device Scaling on Time-domain Voltage-domain Dynamic Range
- A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing