Fan Yibo | State Key Lab Of Asic And System Fudan University

スポンサーリンク

概要

• FAN Yiboの詳細を見る
• 同名の論文著者
• State Key Lab Of Asic And System Fudan Universityの論文著者

関連著者

• Fan Yibo

  State Key Lab Of Asic And System Fudan University

• ZENG Xiaoyang

  State Key Lab of ASIC & System, Fudan University

• Zeng Xiaoyang

  State Key Lab Of Asic And System Fudan University

• Shen Weiwei

  State Key Lab Of Asic And System Fudan University

• Shen Sha

  State Key Lab of ASIC and System, Fudan University

• Zeng Xiaoyang

  State Key Lab. Of Asic & System Fudan University

• ZENG Xiaoyang

  State Key Lab of ASIC and System, Fudan University

• GOTO Satoshi

  IPS, Waseda University

• FAN Yibo

  State Key Lab. of ASIC & System, Fudan University

• Fan Yibo

  State Key Lab. Of Asic & System Fudan University

• Han Jun

  State Key Laboratory For Advanced Metals And Materials University Of Science & Technology Beijing

• Yu Zhiyi

  State Key Lab. Of Asic And System Department Of Microelectronics Fudan University

• ZENG Xiaoyang

  State Key Lab. of ASIC & System, Fudan University

• SHEN Weiwei

  State Key Lab of ASIC and System, Fudan University

• FAN Yibo

  State Key Laboratory of ASIC & System, Fudan University

• Zhang Yuejun

  Institute of Circuits and Systems, Ningbo University

• Wang Pengjun

  Institute of Circuits and Systems, Ningbo University

• LIU Jialiang

  College of Information Science and Engineering, Shandong University of Science and Technology

• ZHANG Dexue

  College of Information Science and Engineering, Shandong University of Science and Technology

• CHEN Xinhua

  College of Information Science and Engineering, Shandong University of Science and Technology

• Zhong Huibo

  State Key Lab of ASIC and System, Fudan University

• HAN Jun

  State Key Laboratory of ASIC & System, Fudan University

• ZHANG Zhang

  Electronics and Apply Physical School, Hefei University of Technology

もっと見る 閉じる

著作論文

• A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder
• Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC
• A 64Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4K × 2K Applications
• An 8×8/4×4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4K×2K H.264/AVC Encoder
• A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4K×2K Applications
• Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65nm CMOS
• A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design
• A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

スポンサーリンク