Yu Wenjian | Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te
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Dept. Of Computer Science And Technology Tsinghua National Laboratory For Information Science And Te | 論文
- Low Power Gated Clock Tree Driven Placement
- Efficient Power Network Analysis with Modeling of Inductive Effects
- Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
- Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
- Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration(VLSI Design Technology and CAD)