Sakamoto Takuya | The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive
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The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive | 論文
- A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance(Special Section on VLSI Design and CAD Algorithms)
- LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression(Special Section on VLSI Design and CAD Algorithms)
- Computational Complexity Analysis of Set-Bin-Packing Problem(Special Section on Discrete Mathematics and Its Applications)
- Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan(Special Section on Discrete Mathematics and Its Applications)
- Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture (Special Section on VLSI Design and CAD Algorithms)