Murotani Tatsunori | Ulsi Device Development Laboratories Nec Corporation

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著作論文

Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hierarchical Word-Line Architecture for Large Capacity DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs (Special Issue on ULSI Memory Technology)

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