Hierarchical Word-Line Architecture for Large Capacity DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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概要

• 論文の詳細を見る

• The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

• 社団法人電子情報通信学会の論文
• 1997-04-25

著者

• Takada Masahide

  Ulsl Systems Development Laboratories Nec Corporation

• Murotani Tatsunori

  Ulsi Device Development Laboratories Nec Corporation

• SUGIBAYASHI Tadahiko

  ULSI Device Development Laboratories, NEC Corporation

• Sugibayashi Tadahiko

  Ulsi Device Development Laboratories Nec Corporation

関連論文

• Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
• Hierarchical Word-Line Architecture for Large Capacity DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
• A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs (Special Issue on ULSI Memory Technology)

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