Kaneko T | Seiko Epson Corp. Nagano Jpn
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概要
Seiko Epson Corp. Nagano Jpn | 論文
- High-Performance Polyclystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process
- Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization(Electronic Displays)
- High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by μ-Czochralski Process(Electronic Displays)
- Extraction of Trap Densities at Front and Back Interfaces in Thin-Film Transistors
- High-Quality Gate-SiO_x and SiO_x/Si Interface Formation at Low Temperature Using Plasma-Enhanced Chemical Vapor Deposition