井上 聡 | Frontier Device Research Center Seiko Epson Corporation
スポンサーリンク
概要
Frontier Device Research Center Seiko Epson Corporation | 論文
- Extraction Technique of Trap Density at Grain Boundaries in Polycrystalline-Silicon Thin-Film Transistors with Device Simulation
- High-Performance Polyclystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process
- High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by μ-Czochralski Process(Electronic Displays)
- 表側と裏側の絶縁膜界面にトラップ準位をもつポリシリコン薄膜トランジスタのデバイスシミュレーション(ディスプレイ-IDW'03関連-)
- High-Quality Gate-SiO_x and SiO_x/Si Interface Formation at Low Temperature Using Plasma-Enhanced Chemical Vapor Deposition