Miyoshi Seiro | Microelectronics Engineering Laboratory, Toshiba Corporation
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概要
Microelectronics Engineering Laboratory, Toshiba Corporation | 論文
- A 1.5 GHz CMOS Low Noise Amplifier
- Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 μm MOSFETs
- Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs
- Reliable High-k TiO_2 Gate Insulator Formed by Ultrathin TiN Deposition and Low Temperature Oxidation
- (Ba, Sr)TiO_3 Stacked Capacitor Technology for 0.13μm-DRAMs and Beyond