Through Silicon Via Fabrication with Low-\kappa Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

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概要

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• Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal--oxide--silicon (MOS) capacitor structure. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved and lined with low-\kappa material with an effective dielectric constant of {\sim}2.8. Low-\kappa liner with conformal step coverage is successfully achieved in our fabrication process. Based on electrical measurement, it is found that the integration of the low-\kappa liner reduces the TSV capacitance by {\sim}27.6% as compared with the conventional plasma-enhanced tetraethylorthosilicate (PETEOS) oxide liner. In addition, current--voltage (I--V) measurement is carried out to monitor and study the leakage of the low-\kappa liner. No abrupt breakdown is observed until at least at an electric field of 3 MV/cm which corresponds to 60 V. Annealing of the TSV structure in forming gas (N2/H2) at 350 °C for 30 min successfully reduces the leakage current density by {\sim}1.6\times, to a mid-distribution value of {\sim}6.8\times 10^{-6} A/cm2.

• 2012-04-25

著者

• Li Hong

  Institute Of Immunological Science Hokkaido University

• Tan Chuan

  Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798

• Gao Shan

  Institute of Microelectronics, ASTAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685

• Li Hong

  Institute of Microelectronics, ASTAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore 117685

• Zhang Lin

  Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798

• Lim Dau

  Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798

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