Quantum Compact Model of Drain Current in Independent Double-Gate Metal--Oxide--Semiconductor Field-Effect Transistors
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概要
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A continuous compact model of drain current in independently driven double-gate (IDG) metal--oxide--semiconductor field-effect transistors (MOSFETs) is presented. The model describes drift-diffusion transport and is continuous over all operation regimes, which makes it very suitable for implementation in circuit simulators. Our approach takes into account two-dimensional (2D) electrostatics and vertical carrier quantum confinement in the channel through the inversion charge evaluated quantum-mechanically. The model effectively reproduces the threshold voltage and the current modulation by the back-gate bias, as well as the quantum confinement effects on the inversion charge. A full 2D quantum--mechanical numerical simulation code (solving the 2D Poisson equation self-consistently coupled with the 1D Schrödinger equation) is used to validate the model. The model is shown to fit with good accuracy the numerically simulated quantum drain current in double-gate devices with either independent or connected gates.
- 2011-02-25
著者
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Moreau Mathieu
IM2NP, CNRS (UMR 6242), Bât. IRPHE, 49 rue Joliot-Curie, BP 146, F-13384 Marseille Cedex 13, France
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Autran Jean-Luc
IM2NP, UMR CNRS 6242, 49 rue Joliot-Curie, BP 146, F-13384 Marseille Cedex 13, France
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Munteanu Daniela
IM2NP, CNRS (UMR 6242), Bât. IRPHE, 49 rue Joliot-Curie, BP 146, F-13384 Marseille Cedex 13, France
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Autran Jean-Luc
IM2NP, CNRS (UMR 6242), Bât. IRPHE, 49 rue Joliot-Curie, BP 146, F-13384 Marseille Cedex 13, France
関連論文
- Impact of (Quasi-)Ballistic Transport on Operation of Complementary Metal--Oxide--Semiconductor Inverters Based on Fully-Depleted Silicon-on-Insulator and Nanowire Devices
- Quantum Compact Model of Drain Current in Independent Double-Gate Metal--Oxide--Semiconductor Field-Effect Transistors
- Simulation Analysis of Quantum Confinement and Short-Channel Effects in Independent Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors
- Simulation of Gate Tunneling Current in Metal–Insulator–Metal Capacitor with Multi layer High-$\kappa$ Dielectric Stack Using the Non-equilibrium Green’s Function Formalism