Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance

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概要

• 論文の詳細を見る

• We propose a stress-controlled fabrication process for shallow trench isolation (STI) that can reduce stress-originated leakage current. In this paper, the relationships between the electrical characteristics of a transistor and the STI fabrication process parameters were obtained by measurement. Direct measurements of mechanical strain around an STI structure were executed by convergent beam electron diffraction (CBED) analysis, and mechanical strain was simulated by the finite element method (FEM). Transmission electron microscopy (TEM) analysis was also performed. It was revealed that the undesirable leakage current in a transistor was caused by a dislocation in crystal silicon, which was induced by tensile strain perpendicular to the silicon surface. We also found that the mechanical strain is controllable by optimizing the amount of recess of the gap-fill oxide in the STI structure after chemical mechanical polishing (CMP).

• 2010-02-25

著者

• Keisuke Tsukamoto

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Fukumoto Koji

  Renesas Technology Corp., 20-1 Josuihon-cho 5chome, Kodaira, Tokyo 187-8588, Japan

• Kudo Shuichi

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Ogawa Yoshifumi

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Fumihito Ota

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Tetsuya Uchida

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Takashi Takeuchi

  Renesas Technology Corp., 751 Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan

• Toru Koyama

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Junko Komori

  Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan

• Hidekazu Yamamoto

  Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-Honmachi, Amagasaki, Hyogo 661-8661, Japan

• Yoji Mashiko

  Department of Electrical and Electronic Engineering, Oita University, 700 Dannoharu, Oita 870-1192, Japan

• Koji Fukumoto

  Renesas Technology Corp., 20-1 Josuihon-cho 5chome, Kodaira, Tokyo 187-8588, Japan

• Kudo Shuichi

  Renesas Electronics Corporation, 751 Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan

関連論文

• Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance
• Characterizations of NiSi2-Whisker Defects in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with $\langle 110\rangle$ Channel on Si(100)
• Three-Dimensional Visualization Technique for Crystal Defects in High Performance p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Embedded SiGe Source/Drain
• Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique
• Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films
• Suppression of Stress-Induced Voiding by Controlling Microstructure of Cu Electroplated Films

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