An Additional 12% Power Reduction in Practical Digital Chips with a Low-Power Design Using Post-Fabrication Clock-Timing Adjustment

概要

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In order to solve the clock-skew problem, which becomes more and more serious for sub-100 nm processes, we have proposed a post-fabrication clock-timing adjustment technique and have been improving it to expand its applications. Several kinds of test chips have been designed and fabricated, and the promising experimental results obtained for these chips have already been presented in several papers. In this paper, the adjustment technique is applied to practical circuits with a low-power design. Conducted experiments demonstrate an additional reduction in power consumption of 12% even for chips with a low-power design, and the effectiveness of the proposed method is confirmed with actual chips.
2009-04-25