Nanowire Field-Effect Transistor

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概要

• 論文の詳細を見る

• A new processing scheme for the fabrication of sub-100-nm-gate-length vertical nanowire transistors has been developed. InAs transistors with an $11 \times 11$ nanowire matrix and 80 nm gate length have been realized by this process. The gate length is directly controlled via the thickness of the evaporated gate metal and is thus easily scalable. The demonstrated devices operate in depletion mode, and they show a maximum drive current of about 1 mA and a maximum transconductance of 0.52 mS at $V_{\text{g}}=-0.5$ V and $V_{\text{d}}=1$ V.

• 2007-04-30

著者

• Lind Erik

  Solid State Physics Lund University

• Samuelson Lars

  Solid State Physics

• Wernersson Lars-erik

  Solid State Physics Lund University

• Lind Erik

  Solid State Physics, Lund University, Box 118, S-22100 Lund, Sweden

• Löwgren Truls

  QuMat Technologies AB, Stora Fiskaregatan 13E, S-22224 Lund, Sweden

• Ohlsson Jonas

  QuMat Technologies AB, Stora Fiskaregatan 13E, S-22224 Lund, Sweden

• Wernersson Lars-Erik

  Solid State Physics, Lund University, Box 118, S-22100 Lund, Sweden

関連論文

• Operation of InGaAs/InP-Based Ballistic Rectifiers at Room Temperature and Frequencies up to 50 GHz
• Controlled Carrier Depletion around Nano-Scale Metal Discs Embedded in GaAs
• High Tuning-Range VCO Using a Gated Tunnel Diode
• Optimization of Overgrown Ex-Situ Processed GaAs Interfaces for a Resonant Tunneling PBT
• Design of Vertical Nanowire FETs
• Nanowire Field Effect Transistor
• Nanowire Field-Effect Transistor
• InP Hot Electron Transistors with a Buried Metal Gate

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