Degradation Phenomenon of p+ to p+ Isolation Characteristics Caused by Carrier Injection in a High-Voltage Process
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概要
- 論文の詳細を見る
In this study, an investigation for the degradation of p+ to p+ isolation characteristics in a high voltage process with shallow trench isolation was carried out. It could be explained that the degradation phenomenon was caused by carrier injection. In order to improve this, the results of p+ to p+ isolation degradation were determined under different ion implantation conditions and depths and widths of isolation. From these results, it was found that carrier injection mainly occurred at the sidewall of a trench, and the interface trap between Si3N4 and SiO2 was considered to be a dominant factor based on the result of degradation reduction with increasing thickness of sidewall oxide. Consequently, the improvement of the p+ to p+ isolation degradation caused by carrier injection could be achieved by optimizing the dose of a masked lightly doped drain and a field implantation energy.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-11-15
著者
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Park Joo-han
Lsi Process Architecture Lsi Development Team System-lsi Division Samsung Electronics Co. Ltd.
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KIM Sung-Hoan
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd.
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KIM Eun-Soo
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd.
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Jo Sung-il
Lsi Process Architecture Lsi Development Team System-lsi Division Samsung Electronics Co. Ltd.
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Kim Byung-sun
Lsi Process Architecture Lsi Development Team System-lsi Division Samsung Electronics Co. Ltd.
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Lee Soo-cheol
Lsi Process Architecture Lsi Development Team System-lsi Division Samsung Electronics Co. Ltd.
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Choi Chang-sik
Lsi Process Architecture Lsi Development Team System-lsi Division Samsung Electronics Co. Ltd.
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Kim Seong-ho
Lsi Process Architecture Lsi Development Team System-lsi Division Samsung Electronics Co. Ltd.
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Jo Sung-Il
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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Park Joo-Han
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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Kim Eun-Soo
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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Kim Seong-Ho
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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Kim Byung-Sun
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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Kim Sung-Hoan
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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Lee Soo-Cheol
LSI Process Architecture, LSI Development Team, System-LSI Division, Samsung Electronics Co., Ltd, San#24, Nongseo-Lee, Kiheung-Eup, Yongin-Si, Kyungki-Do 449-900, Korea
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