Design Considerations for Low-Power Single-Electron Transistor Logic Circuits

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概要

• 論文の詳細を見る

• We have investigated design considerations for low-power single-electron transistor (SET) logic circuits. Supply-voltage scaling is introduced as a method for reducing the power consumption of SET circuits. A detailed analysis of the effects of supply-voltage scaling is given on the basis of the behavior of a complementary capacitively coupled SET inverter circuit. It has been shown that the hysteresis caused by the supply-voltage-dependent threshold voltage of a SET quickly disappears as the temperature rises, and does not ruin the desired inverting operation at a practical operation temperature. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. From the results of power-delay product and delay time, it has been shown that the supply-voltage scaling should be carried out within 20% of maximum supply-voltage to maintain overall circuit performance.

• Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
• 2001-03-30

著者

• Jeong Yoon-ha

  Electrical And Computer Engineering Division Pohang University Of Science And Technology

• Lee Bong-hoon

  Electrical And Computer Engineering Division Pohang University Of Science And Technology

• Jeong Moon-young

  Electrical And Computer Engineering Division Pohang University Of Science And Technology

• Jeong Moon-Young

  Electrical and Computer Engineering Division, Pohang University of Science and Technology, San-31, Hyoja-dong, Nam-ku, Pohang, Kyungbuk 790-784, Korea

• Jeong Yoon-Ha

  Electrical and Computer Engineering Division, Pohang University of Science and Technology, San-31, Hyoja-dong, Nam-ku, Pohang, Kyungbuk 790-784, Korea

• Lee Bong-Hoon

  Electrical and Computer Engineering Division, Pohang University of Science and Technology, San-31, Hyoja-dong, Nam-ku, Pohang, Kyungbuk 790-784, Korea

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