Multi-Wall Channel Transistor for P-type Metal Oxide Semiconductor Field-Effect Transistor Performance Improvement

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概要

• 論文の詳細を見る

• We demonstrate the enhanced hole mobility of p-channel metal oxide semiconductor field effect transistors (PMOSFETs) using a multi-wall structural channel. Multi-wall channels with a height of 35 nm and a width of 70 nm were prepared at 70-nm half-pitches. The multi-wall channel structure produces a (110) surface channel and a strain produced by polycrystalline silicon (poly-Si) gates. These enhance hole mobilities. The degree of enhancement depends on the wall height. We obtained a 45% increase in hole mobility with a 35-nm-high wall at 0.8 MV/cm.

• Japan Society of Applied Physicsの論文
• 2006-08-25

著者

• Mishima Yasuyoshi

  Silicon Device Laboratories, Device and Material Laboratories, Fujitsu Laboratories, Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan

• Shido Hideharu

  Silicon Device Laboratories, Device and Material Laboratories, Fujitsu Laboratories, Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan

• Fukuda Masatoshi

  Silicon Device Laboratories, Device and Material Laboratories, Fujitsu Laboratories, Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan

関連論文

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• Multi-Wall Channel Transistor for P-type Metal Oxide Semiconductor Field-Effect Transistor Performance Improvement

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