Ramp Slope Built-in-Self-Calibration Scheme for Single-Slope Column Analog-to-Digital Converter Complementary Metal–Oxide–Semiconductor Image Sensor

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概要

• 論文の詳細を見る

• The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal–oxide–semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.

• 2006-02-25

著者

• Lee Yonghee

  System Lsi Division Semiconductor Business Samsung Electronics Corporation

• Jung Wunki

  Department Of Electrical And Electronic Engineering Yonsei University

• Ham Seogheon

  Department Of Electrical And Electronic Engineering Yonsei University

• Lee Dongmyung

  Department Of Electrical And Electronic Engineering Yonsei University

• HAN Gunhee

  Department of Electrical & Electronic Engineering, Yonsei University

• Lee Yonghee

  System LSI Division, Semiconductor Business, Samsung Electronics Corporation, San #24 Nongseo-Ri, Giheung-Eup, Yongin-City, Kyungki-Do, Korea

• Ham Seogheon

  Department of Electrical and Electronic Engineering, Yonsei University, 134 Sinchon-dong, Seodaemun-gu, Seoul, Korea

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