A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop(Electronic Circuits)
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概要
- 論文の詳細を見る
A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3mm^2.
- 一般社団法人電子情報通信学会の論文
- 2004-05-01
著者
-
Han Gunhee
Department Of Electrical And Electronic Engineering Yonsei University
-
Kwon Minho
Department Of Electrical And Electronic Engineering Yonsei University
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LEE Jungyoon
Department of Electrical and Electronic Engineering, Yonsei University
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HAN Gunhee
Department of Electrical & Electronic Engineering, Yonsei University
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- A Time-Interleaved Switched-Capacitor Band-Pass Delta-Sigma Modulator with Recursive Loop(Electronic Circuits)