Linearity enhancement technique of ramp generator for ADC testing
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概要
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This work presents the method to enhance the linearity of ramp generator for ADC testing. Through utilizing the parasitic model of capacitance, we develop an extraction method to estimate parasitic components concerning with linearity of integration for ramp generator. The further use of negative impedance converter provides adjustable negative impedance for compensating redundant parasitic components. The resulted impedance is almost pure capacitance enabling the possibility of very linear current integration for ramp generator. The simulation results show that the proposed method is able to generate very linear ramp signal for constant current source. The differential and integral nonlinearity of ramp signal is almost reduced to one-twentieth of that without compensating.
著者
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Lin Chun
Department Of Chemistry Florida Institute Of Technoloy
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Chen Yu
Department And Graduate School Of Physical Education National Taiwan College Of Physical Education
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Lin Sheng
Graduate School of Engineering Science and Technology, National Yunlin University of Science and Technology
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Lin Chun
Department of Electronic Engineering, National Yunlin University of Science and Technology
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