Low Power Clock Gating for Shift Register

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概要

• 論文の詳細を見る

• A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.

著者

• Kim Nam-soo

  Department Of Agronomy Kangwan National University

• Kim Yeong-seuk

  Department Of Semiconductor Engineering Cbnu

• SOHN Ki-Sung

  Department of Semiconductor Engineering, Chungbuk National University

• HAN Da-In

  Department of Semiconductor Engineering, Chungbuk National University

• BAEK Ki-Ju

  Department of Semiconductor Engineering, Chungbuk National University

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