Effect of High Frequency Noise Current Sources on Noise Figure for Sub-50nm Node MOSFETs

概要

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The downscaling of CMOS technology has resulted in strong improvement in RF performance of bulk and SOI MOSFETs. In order to realize a low-noise RF circuit, a deeper understanding of the noise performance for MOSFETs is required. Thermal noise is the main noise source of the CMOS device for high frequency performance, and is dominated by the drain channel noise, induced gate noise, and their correlation noise. In this work, we measured the RF noise parameter (Fmin, Rn, Γopt) of 45nm node MOSFETs from 5 to 15GHz and extracted noise sources and noise coefficients P, R, and C by using an extended van der Ziels model. We found, for the first time, that correlation coefficient C decreases from positive to negative values when the gate length is reduced continuously with the gate length of sub-100nm. We confirmed that Pucels noise figure model, using noise coefficients P, R, and C, can be considered a good approximation even for sub-50nm MOSFETs. We also discussed a scaling effect of the noise coefficients, especially the correlation noise coefficient C on the minimum noise figure.