Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction (<Special Issue on> Fundamental Aspects and Recent Developments in Multimedia and VLSI Systems)

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概要

• 論文の詳細を見る
• 東北大学の論文

著者

• Hwang Ting-Ting

  Department of Computer Science, National Tsing Hua University

• CHANG An-Chi

  Department of Computer Science, National Tsing Hua University

関連論文

• Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis (Special Issue on Synthesis and Verification of Hardware Design)
• Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction
• Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction ( Fundamental Aspects and Recent Developments in Multimedia and VLSI Systems)

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