Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction

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概要

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• Power optimization has always been an important issue for modern IC design. In this paper, we present a power optimization technique for clock tree by applying multi-bit flip-flops and reducing total wire length. Through merging flip-flops into MBFFs, we effectively reduce power consumption caused by clock buffers. Moreover, by judiciously merging and placing the MBFFs, the total wire length is also significantly reduced. The combined effect of both techniques leads to a strong reduction in total power consumption of the clock network.

• 東北大学大学院情報科学研究科の論文

著者

• Hwang Ting-Ting

  Department of Computer Science, National Tsing Hua University

• CHANG An-Chi

  Department of Computer Science, National Tsing Hua University

関連論文

• Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis (Special Issue on Synthesis and Verification of Hardware Design)
• Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction
• Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction ( Fundamental Aspects and Recent Developments in Multimedia and VLSI Systems)

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