Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• Reducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. In this paper, we consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting "globals" and deriving subfunctions are addressed. Moreover, the Decomposition Don't Cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized.

• 一般社団法人電子情報通信学会の論文
• 1993-09-25

著者

• Wang Kuo-hua

  Department Of Computer Science And Information Engineering National Chiao Tung University

• Hwang Ting-Ting

  Department of Computer Science, National Tsing Hua University

• Chen Cheng

  Department of Computer Science and Information Engineering, National Chiao Tung University

• Chen Cheng

  Department Of Computer Science And Information Engineering National Chiao Tung University

関連論文

• Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis (Special Issue on Synthesis and Verification of Hardware Design)
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