An Asynchronous Commit DMR Architecture for Aggressive Low-Power Fault Toleration

概要

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Dual modular redundancy (DMR) execution is commonly used in many high-end processor platforms to tolerate the increasing transient faults caused by single event effects (SEEs) along the advances of process technology. As the operations must be performed twice to facilitate the comparison based error detection, the power consumption efficiency is always an important issue for dependable systems. To reduce the power consumption, dynamic voltage scaling (DVS), together with Razor FF, have been proposed and well used to lower the voltage to a balancing point for an optimal energy reduction. However, simply combining a DMR and Razor-FF will easily have performance impact as the synchronous committing logic in the traditional DMR architecture does not work well with the dynamic frequency in a Razor FF processor. In this research, we propose a globally asynchronous locally synchronous DMR architecture that uses dedicated clocks on each DMR module. FIFOs and delay buffers are additionally added and well controlled to guarantee the data checking inside this asynchronous system for both soft and timing error. Compared to the traditional synchronous DMR system, we can have around 10% performance improvement by this asynchronous committing scheme when a same power reduction ratio is assumed. On the other hand, voltage can be aggressively tuned in either DMR module to achieve 12% better MIPS/W without major down-gradation of the performance.
2014-02-27