Exploiting Efficiency of Redundant Executions on an FU Array

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概要

• 論文の詳細を見る

• We introduce an error tolerable processor to perform duplicated executions by supporting an Explicitly REdundant VLIW Architecture (EReLA). EReLA extends the conventional VLIW ISA and provides special data sanity check (DSC) instructions to help compilers insert fail-safe mechanisms into binaries. As the redundant execution will lengthen the data path, we further study a scheme to employ a functional unit (FU) array based accelerator to sufficiently cover the possible performance impact. Our results show that the explicitly denoted fail-safe mechanisms in EReLA can work best with the FU array to tolerate both soft and hard errors. By properly mapping extended binaries onto the FU array, the processor can maintain its loop iteration-based throughput, which indicates a negligible performance cost.

• 2011-03-03

著者

• Jun Yao

  Nara Institute of Science and Technology

• Yasuhiko Nakashima

  Nara Institute of Science and Technology

• Jun Yao

  Nara Institute Of Science & Technology

• Yasuhiko Nakashima

  Nara Institute Of Science & Technology

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• Comparison of emulation oriented 8-bit ISA with 6502 ISA for an ARM emulator
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