A Multi-Band Burst-Mode Clock and Data Recovery Circuit(Analog and Communications,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)
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概要
- 論文の詳細を見る
A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32Mbps, 1244.16Mbps, 622.08Mbps, and 155.52Mbps, which are specified in a gigabit-capable passive optical network (GPON). A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18μm CMOS process. Its active area is 0.41mm^2 and consumes 70mW including I/O buffers from a 1.8V supply.
- 社団法人電子情報通信学会の論文
- 2007-04-01
著者
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Liu Shen-iuan
Graduate Institute Of Electronics Engineering & Department Of Electrical Engineering National Ta
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Liu Shen-iuan
Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw
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LIANG Che-Fu
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Tai
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HWU Sy-Chyuan
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Tai
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Hwu Sy-chyuan
Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw
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Liang Che-fu
Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw
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