All-Digital Clock Deskew Buffer with Variable Duty Cycles(<Special Section>Analog Circuit and Device Technologies)

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概要

• 論文の詳細を見る

• An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35μm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400MHz to 600MHz.

• 社団法人電子情報通信学会の論文
• 2006-06-01

著者

• Liu Shen-iuan

  Graduate Institute Of Electronics Engineering & Department Of Electrical Engineering National Ta

• Liu Shen-iuan

  Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw

• KAO Shao-Ku

  Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Tai

• Kao Shao-ku

  Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw

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