A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs(PLL, <Special Section>Analog Circuit and Device Technologies)

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概要

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• A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-μm CMOS technology and occupies a core area of 1 mm^2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.

• 2005-06-01

著者

• Liu Shen‐iuan

  National Taiwan Univ. Taipei Twn

• Liu Shen-iuan

  Graduate Institute Of Electronics Engineering & Department Of Electrical Engineering National Ta

• YANG Rong-Jyi

  Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National

• Yang Rong-jyi

  Graduate Institute Of Electronics Engineering And The Department Of Electrical Engineering National

• Yang Rong-jyi

  Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw

• Liu Shen-iuan

  Graduate Institute Of Electronics Engineering And The Department Of Electrical Engineering National

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