Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC(<Special Section>Analog Circuits and Related SoC Integration Technologies)
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概要
- 論文の詳細を見る
A new digital calibration scheme for a 14bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3bit DAC and a 6bit DAC. Nevertheless, a large calibration range is achieved. Full 14bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83dB (57dB) for signals of 24kHz (98MHz) at 200Msps update rate.
- 社団法人電子情報通信学会の論文
- 2007-06-01
著者
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Matsuzawa Akira
Tokyo Institute Of Technology
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Matsuzawa Akira
Tokyo Inst. Of Technol. Tokyo Jpn
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Ikeda Yusuke
Tokyo Institute Of Technology
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