A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC

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概要

• 論文の詳細を見る

• We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

• （社）電子情報通信学会の論文
• 2010-11-01

著者

• Kawabata Masayuki

  Advantest Laboratories

• KURAMOCHI Yasuhide

  Advantest Laboratories

• Matsuzawa Akira

  Tokyo Inst. Of Technol. Tokyo Jpn

• Matsuzawa Akira

  Tokyo Institute Technology

• Kawabata Masayuki

  Advantest Corporation Gunma R&d Center

• UEKUSA Kouichiro

  Advantest Corporation, Gunma R&D Center

• Uekusa Kouichiro

  Advantest Corporation Gunma R&d Center

• Kuramochi Yasuhide

  Advantest Corporation Gunma R&d Center

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